In the field of communications, the need for high-speed transmission of data including video and audio has continued to increase. Moreover, in addition to the demand for higher bandwidth, there has also been an increased need for various types of services that employ different protocols. For example, certain customers (e.g., companies providing voice services) of high-speed networks want to operate on a Time Division Multiplexing (“TDM”) Network, which combines different data streams, such as voice traffic, such that each data stream is assigned a time slot within the combined data stream. Moreover, other customers of high-speed networks may desire to transport data employing packet-based data streams, which do not have dedicated timeslots to given packets. Examples of the types of packets that can be placed into such data streams include Asynchronous Transfer Mode (“ATM”), Internet Protocol (“IP”), Frame Relay, Voice Over IP, and Point-to-Point Protocol (“PPP”). Typically, TDM based Synchronous Optical Network (“SONET”) and Synchronous Digital Hierarchy (“SDH”) technologies can transport this packet data traffic in today's market.
Network elements are used to route or switch data of these different protocols across such high-speed networks. Moreover, these network elements typically include a number of line cards that include a number of ports to receive and transmit this data of different standards and protocols. These line cards typically contain a number of circuits and memory for storing and provisioning of the transferred data. In addition, these network elements typically include a number of control cards that include a number of ports to receive and transmit data to the line cards. Data of different transfer rates, i.e., within different clock domains, may be transmitted through and among the various network elements.
Sometimes, data of one traffic rate, e.g., DS1, is bundled for transmission within a signal of a higher traffic rate, e.g., DS3, requiring several interim conversion processes. Historically first-in-first-out data registers (“FIFOs”) have been used to store and transmit data within portions of network elements. When storing and transferring data within one clock domain, a synchronous FIFO is used. When storing and transferring data between two clock domains, an asynchronous FIFO is used. An asynchronous FIFO stores the data and transmits the data in a different clock domain. Accordingly, when data traffic of one rate, e.g., DS3, is converted into a different rate, e.g., SONET, an asynchronous FIFO is employed for the loading and unloading of data. Control circuitry containing flip-flops, pointers, double-sync logic, gray code conversion tables, etc. are used to provision the data through the FIFOs.
A phase-locked loop is used to generate a clock by which a FIFO is unloaded, and generally consists of a frequency phase detector, a low-pass filter, and a voltage controlled crystal oscillator (“VCXO”). Specifically, a signal from the FIFO regarding its depth is transmitted to a phase-locked loop. The phase-locked loop generates a clock signal, which is then transmitted back to the FIFO, and is used by the FIFO as the clock by which the FIFO unloads.
In a phase-locked loop, the loop gradually adjusts the VCXO's outputted clock rate (i.e., speeds it up or slows it down) in an attempt to bring the depth of the FIFO to its mid-point without making abrupt changes in the clock signal rate or causing the depth to wander around the correct rate. For example, if the depth of the FIFO is below its mid-point, the VCXO is slowed down (resulting in a slowing of the outputted clock signal) so that the FIFO unloads slower and thus, fills towards its mid-point; if the depth of the FIFO is above its mid-point, the VCXO is sped up (resulting in an increase in the rate of the outputted clock signal) so that the FIFO unloads faster and thus, empties towards its mid-point. The speed of the VCXO is adjusted in relation to the FIFO depth in order to remain at an operating speed that keeps the amount of data in the FIFO roughly equidistant from the extremes of the FIFO (i.e., underflowing (no data in the FIFO when data must be sent) and overflowing (FIFO is full and data is arriving faster than the data is sent)). Ideally, the FIFO is at the midpoint of its depth range, and the VCXO is operating at the midpoint of its speed range, enabling both to adjust to FIFO depth increases or decreases.
Phase-locked loops take time to adjust their operating speed. If they are permitted to follow the depth of the FIFO, inaccuracies of data arrival time would cause unacceptable irregularities in the resulting rate of the clock signal. Therefore, the response of the VCXO to error signals must be slowed. This slowing is performed by the low-pass filter. However, if the FIFO is permitted to remain too far from half-full, or the response of the VCXO to deviations of the amount of data in the FIFO from the desired amount is excessively slowed, a sudden and sustained change in the rate of input to the FIFO could cause the FIFO to overflow or underflow because the speed of the VCXO (and thus the resulting clock signal to unload the FIFO) did not change fast enough.